Certain portable applications, including wireless handsets, notebook computers and personal digital assistants (PDAs), often employ circuitry which runs on two or more different voltage levels. For example, circuitry utilized with such portable applications may be configured so that a portion of the circuitry, such as, for example, input/output (IO) buffers, runs at a higher voltage level (e.g., about 3.3 volts), while another portion of the circuitry, such as, for example, core logic, runs at a substantially lower voltage level (e.g., about 1.0 volt). This difference in voltage levels often necessitates the use of a voltage level translator circuit for interfacing between the multiple voltage levels.
Conventional voltage level translator circuits have generally been found to be unreliable and/or at least partially inoperable at certain process, voltage and/or temperature (PVT) conditions, and/or to consume substantial direct current (DC) power. In certain portable applications, it is not uncommon to employ an appreciable number (e.g., hundreds) of voltage level translator circuits, and therefore the overall DC power consumption attributable to these voltage level translator circuits can be excessive. Moreover, for portable applications, power is typically supplied by a battery having a limited operating life. Consequently, in order to extend the operating life of the battery, it would be advantageous to eliminate or substantially reduce the amount of DC power consumed by the voltage level translator circuit(s).
There exists a need, therefore, for an improved voltage level translator circuit for interfacing between multiple voltage levels that does not suffer from one or more of the problems exhibited by conventional voltage level translator circuits.